Field of the Invention
This invention relates generally to multi-chip modules and their fabrication, and, more particularly, to a chip connection layer having integral power and ground planes.
Description of the Related Art
In the packaging of very large scale integrated circuit chips, much space is taken up by connections between integrated circuit (IC) chips and adjacent chips and/or other circuit components. This makes the packaging of integrated circuit chips and electronic components based thereon larger than necessary. As a result of this, many approaches have been taken toward development of so-called wafer scale integration processes. However, the efforts expended in these directions have generally resulted in limited yield. Because a number of chips or dies on a wafer are often found to be defective, the number of wafers produced that are completely usable is generally lower than desired. Accordingly, an approach that would enable construction of wafer scale integrated circuit packages from individual, easily testable integrated circuit chips would be desirable.
In prior high density interconnect (HDI) techniques, a polymer film overlay covers a plurality of integrated circuit chips adjacent to one another on an underlying substrate. The polymer film provides an insulated layer upon which is deposited a metallization pattern for interconnection of individual circuit chips. A significant advantage of those embodiments is the ability to remove one or more of the interconnection layers so as to provide various arrangement and testing capabilities.
Methods for performing a HDI process using overlays are described in Eichelberger et al., U.S. Pat. No. 4,783,695, issued Nov. 8, 1988, and in Eichelberger et al., U.S. Pat. No. 4,933,042, issued Jun. 12, 1990, both of which are commonly assigned and hereby incorporated by reference. Additionally, it is desirable to provide via openings or apertures in the polymer film overlay so as to be able to provide electrical connection between various parts of a chip or between several chips. Commonly assigned Eichelberger et al., U.S. Pat. No. 4,894,115, issued Jan. 16, 1990, which is hereby incorporated herein by reference, discloses embodiments for providing such apertures. Furthermore, methods for gaining access to and replacing a defective integrated circuit chip are disclosed in Eichelberger et al., U.S. Pat. No. 4,878,991, issued Nov. 7, 1989, and Wojnarowski et al., U.S. Pat. No. 5,154,793, issued Oct. 13, 1992, which are commonly assigned and hereby incorporated by reference.
In prior interconnection techniques, chip wells are often mechanically milled into substrates. Aforementioned Fillion et al., U.S. Pat. No. 5,353,498 discloses a method of fabricating an HDI substrate by molding plastic around chips placed on a film, thus eliminating the milling process and providing a planar surface without moats between chips and the substrate. The time and expense involved in fabricating modules of this configuration is proportional to the area of the substrate and the number of layers of interconnection. Power and ground lines typically require separate layers of interconnection. Thus it would be desirable to have an integral power and ground structure for reducing module processing steps.